1. Field of the Invention
This invention relates to a buffer circuit for a semiconductor integrated circuit. In particular it relates to an improved buffer circuit wherein entry of noise into the in-chip power source is prevented when the output signal is changed.
2. Description of the Related Art
In semiconductor memories, a series of control signals are generated internally for selecting specific memory cells on receipt of an external signal. In such cases, an initial signal is generated first in response to a change of the external signal. In general, a series of signals are sequentially generated with a certain delay between successive signals. FIG. 1 shows a conventional example of a clock pulse generator. It generates signals of this type using NMOS (N channel insulated gate) transistors. FIG. 2 shows a conventional example using CMOS (complementary insulated gate) transistors. In FIG. 1, .phi.n-1 is the input signal. .phi.p is the precharge signal. .phi.n is the output signal. Vcc' and Vss' are the power source potential and ground potential within the integrated circuit chip. BUF is a buffer constituting the final output stage. It consists of two N-channel enhancement type transistors Q1 and Q2 for load and drive. N1 and N2 are the input nodes of this buffer BUF. N3 is the output node of this buffer BUF. C1 is the load capacitance present between this output node N3 and the in-chip power source node. C2 is the load capacitance present between this output node N3 and the in-chip ground node. In FIG. 2, .phi.n-1 is the input signal, .phi.n is the output signal, Vcc' and Vss' are the source potential and ground potential within the chip, BUF' is a buffer constituting the final output stage. Buffer BUF' includes a P channel enhancement type transistor Q1' for load and an N channel enhancement type transistor Q2' for drive. N1' and N2' are the input nodes of this buffer BUF'. N3' is the output node of this buffer BUF. C1' is the load capacitance that exists between this output node N3' and the in-chip power source node. C2' is the load capacitance that exists between this output node N3' and the in-chip ground node.
The construction and operation of the buffers of FIG. 1 and FIG. 2 is well known, and so it will not be described in detail. The signal waveforms of the main nodes produced by changes in the logic level of the respective input signals .phi.n-1 are shown in FIG. 3 and FIG. 4. In the case of an NMOS circuit, when precharge signal .phi.p becomes potential Vss' and input signal .phi.n-1 rises to potential Vcc', after a certain delay, output signal .phi.n rises to potential Vcc'. When input signal .phi.n-1 falls to potential Vss' and precharge signal .phi.p rises to potential Vcc', output signal .phi.n falls to potential Vss'. In the case of a CMOS circuit, rise and fall of output signal .phi.n occur after a certain delay after the rise or fall of input signal .phi.n-1. In both these circuits, an output signal .phi.n having the capacity to charge or discharge large load capacitances C1 and C2 or C1' and C2' is output with a certain time delay in response to changes in input signal .phi.n-1.
However, in the case of a dynamic random access memory (RAM), to precharge portions where the number of repeated patterns of the bit line or decoder in the precharging cycle is large, the clock generator for generating the precharging signal must charge or discharge a fairly large load capacitance. FIG. 5 shows the circuit of the final output stage buffer of a clock generator used in such cases. In this Figure, in the case of an NMOS type circuit, load transistor Q1 is an N channel transistor, and in the case of a CMOS type circuit it is a P channel transistor. Drive transistor Q2 is an N channel transistor. N1 and N2 are input nodes. N3 is an output node. Vcc and Vss are the power source potential whereby a constant voltage is supplied from outside the chip, and ground potential, respectively. The impedance component 1 includes an inductive component L and resistive component R possessed by the power source line in the chip. The impedance component 2 includes an inductive component L and resistive component R possessed by the ground potential line in the chip. Vcc' and Vss' are the in-chip power source potential and ground potential. The load capactance C1 exists between output node N3 and the in-chip power source node. The load capacitance C2 is present between output node N3 and the in-chip ground node. The reference symbol i represents the output current of this buffer circuit. .phi.n is the output signal of this buffer circuit.
Thus, if an impedance component 1 of the in-chip power source line and an impedance component 2 of the in-chip ground line are present, as described above, large noise signals will be introduced into the in-chip Vcc' and Vss' potentials. This will be described in detail below.
In general, if a current i flows in an impedance component having a resistive component R and inductive component L in series, this produces a voltage drop iR+L di/dt in the direction in which this current i flows. Consequently, in the impedance of FIG. 5, when the output singal .phi.n rises, transistor Q1 goes ON and transistor Q2 goes OFF. The charge of load capacitance C1 moves between the electrodes through transistor Q1, which is now ON, and does not flow into impedance component 1. In contrast, the charge of load capacitance C2 is then supplied from outside-chip power source Vcc through this impedance component 1 and transistor Q1, which is now ON. Since transistor Q2 is OFF, this charge flows to the outside-chip ground power source through impedance component 2. Also, when output signal .phi.n falls, transistor Q1 is OFF and transistor Q2 is ON. The charge of load capacitance C2 moves across the electrodes through transistor Q2 and does not flow into impedance component 2. In contrast, the charge of load capacitance C1 is then discharged to the outside-chip ground power source through transistor Q2, which is now ON, and through impedance component 2. Since transistor Q1 is OFF, a charge flows in from outside-chip power source Vcc through impedance component 1. The changes in this current i and in its time derivative di/dt when the output signal .phi.n rises and falls in this way are shown in FIG. 6(a). This introduces a noise signal into the in-chip potential Vcc' and ground potential Vss' causing them to change in the way shown in FIG. 6(b). That is, when the output signal .phi.n does not change, the amplitudes of the in-chip power source voltage and outside-chip power source voltage are the same. However, when the output signal .phi.n changes, a noise signal is superimposed on the in-chip power source, producing a fluctuation in the voltage amplitude. It should be noted that although for the sake of simplicity in illustration, the impedance component has been modelled as a distribution of a pure resistive component R and inductive component L, in fact, the distribution of these R and L and the distribution of the load capacitances C1 and C2 is complex. This in turn complicates the amplitude change waveform of the in-chip power source voltage.
As explained above, when a change occurs in the in-chip voltage, for the circuits in the chip this is the same as a large fluctuation in the power source. This, therefore, lowers the power source voltage operating margin of the chip as a whole by a very significant amount. In extreme cases, it may lead to spurious operation or failure of operation of the circuitry in the chip. This tendency becomes more severe as the discharging/charging capacity constituting the load of the buffer output signal becomes greater. This occurs with increasing degrees of circuit integration (i.e. for example, with increased memory capacity of an integrated circuit memory), with increase in the resistive component or inductive component of the in-chip interconnections, and also with increasing speed of circuit operation.